Parity Coding

Name: Parity Coding
Status: complete
Affiliation: 18-240 Structure and Design of Digital Systems Lab 1
Group members: Arlene
Start: 1/23/2011
End: 1/27/2011

Description: Implements parity coding, which is a safety caution that adds one bit to a code word. This extra bit allows error detection when any one bit in the code word is corrupted. In an even parity code, the parity bit is set so there is an even number of 1 bits in the code word, while in an odd parity code, the opposite occurs. An interesting fact to note is that the odd parity bit can be computed as the negation of the even parity bits. The primary limitation with parity coding is that it can be assumed to be correct IFF single-bit errors are the only possible sources of corruption.

Notable issues with parity coding:
-Does not tell you how many errors
-Does not tell you where the errors are
-Can miss errors if they are of the correct parity

What I learned:
-introduction to System Verilog
-parity coding
-assigning logic inputs and outputs to pins on the hardware (xilinx spartan 3)


Asserts 1 when code word is inconsistent. In the video, I increment the input from 0 to 63.