Name: CMOS Inverter Layout
Status: complete
Affiliation: 18-220 Electronic Devices and Analog Circuits Lab 3
Group members: Frank
Start: 2/9/2011
End: 2/9/2011
Description: Using L-Edit (layout editor), designed a minimal CMOS inverter using n-channel and p-channel transistors. The transistor depiction of an inverter is as follows:
We were given the constraints of λ = .5 uM, Z_n = 20 uM = 40 λ, and Z_p = 60 uM = 120 λ. In both channels, L = 2 (minimum possible L) because there were no additional constraints on it.
Lessons Learned:
-introduction to layout design in L-Edit
-minimal design rules
-using DRC to check whether or not I pass minimal design rules
-taking layout cross sections
-testing separate components helps identify which part of your layout is wrong - this applies to EVERYTHING, including unit testing, classes, modules, etc.
finalized inverter layout